In applications such as providing a data communication link between two Application Specific Integrated Circuits (ASICs) in a local backplane of a computing system, very high data rates may be required, e.g. an average data rate of at least 4.8 Giga bits per second (Gbps). The data link may be 64 bits wide.
Of the various possibilities for implementing such a link, it is possible to provide an interface that transfers data from the transmitting ASIC to the receiving ASIC as a single parallel word with a synchronising clock signal running at the system clock rate CK, say 78 MHz. However, for a data word of 64 bits to achieve a data transfer rate of 4.8 Gbps this would require 65 device pins, which for many applications would be either impractical or too costly to provide in the ASICs.
A synchronous interface could be used using a smaller number of pins, by multiplexing a 64 bit wide data word N times onto W bits (=64/N) and by providing a synchronising clock. However with a clock signal running at 78 MHz, the bandwidth would be reduced to W*CK=BW/N, which would give an unacceptably slow data transfer rate.
In order to achieve a bandwidth of 4.8 Gbps, the transfer rate may be multiplied N times. A synchronous interface which has a resultant Transfer Clock, N * CK, of less than 200 MHz may be practical. Above 200 MHz, which would be necessary to achieve the desired transfer rate of 4.8 Gbps, each data bit would be valid for a maximum of 5 ns, reducing further when rise-fall times of the interconnect signals and input/output buffers are included. The task of achieving a robust design, ensuring that all W bits are aligned such that the synchronising clock can always capture valid data bytes at the receiving ASIC, is far from trivial.